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◆ Writing 6502 Assembly › Setup

Setup

This page assumes you have completed f03b. Your breadboard has a working 6502, a 32KB ROM at 8000–8000–FFFF, and 32KB of RAM at 0000–0000–7FFF. You have run the test program — the CPU loops at reset, the address-line LEDs move, the thing is alive. That is the starting point.

f03c adds a W65C22 Versatile Interface Adapter (VIA) chip. The VIA gives the CPU programmable I/O pins: it is how the 6502 talks to the world. By the end of this chapter those pins will drive a LED, read a button, and push audio through a piezo buzzer.

The address decode change

Adding the VIA forces a wiring change you need to make before anything else. In f03b, the RAM chip was selected by A15 going low (A15=0 means 0000–0000–7FFF, which is the RAM half of the address space). That worked when RAM was the only chip in the lower half. Now the VIA needs a slice of that space too, so the decode has to become more precise.

The new layout divides the lower half by A14:

  • $0000–$3FFF: RAM — A15=0, A14=0
  • $4000–$7FFF: VIA — A15=0, A14=1
  • $8000–$FFFF: ROM — A15=1

To implement this, change the RAM chip-enable line. Pull the wire that currently runs from RAM CE# to A15 and move it to A14 instead. RAM is now selected when A14 is low, which gives it the lower quarter of the address space (0000–0000–3FFF). That is more than enough for zero-page variables, the stack, and any RAM the programs in this chapter need.

Wiring the VIA

The W65C22 is a 40-pin DIP. Place it on the breadboard with its notch oriented consistently with the 6502 (check the datasheet pinout before you seat it — inserting a chip backwards destroys it).

Connect the VIA to the rest of the circuit as follows.

Data bus. The VIA's D0–D7 pins connect directly to the CPU's D0–D7 data bus lines. These are the same lines already running to the ROM.

Register select. The VIA has four register-select pins RS0–RS3. Connect them to CPU address lines A0–A3 respectively. The VIA uses these four bits to decide which of its internal registers the CPU is reading or writing. With RS0–RS3 connected to A0–A3, each VIA register maps to a different address in the 4000–4000–7FFF range — 4000isPORTB,4000 is PORTB, 4001 is PORTA, 4002isDDRB,4002 is DDRB, 4003 is DDRA.

Clock and control. Connect VIA PHI2 to CPU pin 37 (the PHI2 clock output). Connect VIA RWB to CPU pin 34 (the RWB line that signals whether the CPU is reading or writing). Connect VIA RESB to CPU pin 40 (the reset line), so the VIA resets together with the CPU.

Chip select. The VIA has two chip-select inputs:

  • CS1 is active HIGH — the VIA is selected when this pin is high. Connect CS1 to CPU A14.
  • CS2B is active LOW — the VIA is selected when this pin is low. Connect CS2B to CPU A15.

With this wiring the VIA is active when A14=1 and A15=0 — exactly the 4000–4000–7FFF window. At any address outside that window at least one of the two conditions fails, so the VIA ignores the bus.

Power. Connect VIA VCC to +5V and VIA GND to the ground rail.

That is the hardware side. The breadboard now has three active chips: the 6502, the ROM, and the VIA, with RAM in its new position.

Verify vasm

If you followed f03b/00, vasm is already installed. Confirm it is still on your path:

vasm6502_oldstyle --version

You should see a version string. If the command is not found, go back to f03b/00 and reinstall it — the assembler is the only build tool this chapter needs.

Working directory

Create a fresh directory for this chapter's programs:

mkdir ~/f03c-practice
cd ~/f03c-practice

All five source files go here. Each one gets assembled to a .bin, burned to the EEPROM with minipro, and tested on the board before moving to the next.