The address bus is the CPU asking "I want what is at this address." The data bus is the answer: 8 wires, D0–D7, carrying a single byte in either direction between the CPU and whichever chip is selected. When the CPU fetches an instruction, the ROM puts the opcode byte on those eight wires. When the CPU writes to memory, the CPU puts a data byte on those wires and the RAM latches it.
Every instruction fetch, every operand load, every store — all of them cross these eight wires. A single broken connection here does not cause one instruction to misbehave; it corrupts every instruction that contains a 1 bit in that position, which means the program executes something completely different from what was assembled.
Why the address bus LEDs are sufficient evidence
Before adding a logic probe or an oscilloscope, consider what the
LED pattern from the previous page is actually telling you. The CPU
is repeatedly fetching the same three-byte instruction from 8001, 8000. That sequence requires the CPU to have read three valid bytes
from the ROM and decoded them correctly as a jmp instruction. If
any data bus wire were missing or misconnected, the CPU would decode
a different opcode and either crash, execute a NOP sled into
uninitialized memory, or loop on a different instruction at a
different address.
The specific LED pattern you see — A0–A7 cycling through 01, $02 with A15 always high — is proof that D0–D7 are all connected and correct. The data bus is working.
What a broken data bus looks like
It is worth knowing the failure modes anyway, because you will wire this circuit by hand and mistakes happen.
One data wire missing. The CPU reads every byte with that bit forced to 0. For example, if D0 is disconnected, the byte 4C but 80 (hi byte) may be read as 80 or as corrupted values depending on the floating pin's resting voltage. The CPU may jump to a wrong address and execute whatever it finds there — typically an infinite NOP sled if the uninitialized ROM area reads 00. In either case the address LEDs will show a very different pattern from the expected tight loop, usually with all low address bits active rather than just A0–A1–A2 cycling.
One data wire shorted to another. Two bits carry the same value. The opcode is still corrupted, but in a different way. The address LEDs will again show an erratic or unexpected pattern.
One data wire shorted to VCC or GND. That bit is stuck high or low for every byte the CPU reads. The failure looks similar to a disconnected wire.
In all three cases, the diagnostic procedure is the same: measure each data pin on the ROM with a multimeter. Each pin should toggle between 0V and 5V as the CPU loops. A pin stuck at 0V or 5V is your culprit. Trace the wire from that ROM pin to the corresponding CPU pin and look for a missing connection, a bridge to an adjacent tie point, or a broken jumper.
Common mistakes at this stage
Data wires crossed. D0 on the ROM is not always the same physical pin number as D0 on the CPU. Check the datasheet pinout for the AT28C256 and compare against the W65C02S pinout. If you wired by position ("the leftmost data pin on the ROM goes to the leftmost data pin on the CPU") rather than by label, they may be scrambled. Scrambled data bits will still produce some LED activity — the CPU will execute something — but the pattern will be wrong.
A data wire landed on the wrong breadboard row. On a half-size breadboard the tie points are closely spaced. A wire that should be in row 24 may have landed in row 23. Visual inspection is often enough; dragging a fingernail across the wires while looking at the chip pin they enter will catch most errors.
The ROM is not selected. If ROM CE# is floating or stuck high, the AT28C256 does not drive the data bus at all. Its D0–D7 pins go high-impedance, and the CPU reads the floating bus — typically FF is not valid on the 6502 and the CPU will do something undefined. If the address LEDs show very fast random activity or no activity at all, check the NAND gate output on ROM CE#: it should go low when A15 is high.
Once the address LEDs show the correct steady pattern — the tight loop at $8000 visible as A0–A2 cycling — the data bus is confirmed good. Move on to adding RAM.